Write VHDL code for Half Adder using Data Flow Modeling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_HA is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end test_HA;

architecture data_flow_test of test_HA is
begin
sum<= a xor b;
cout<= a and b;
end data_flow_test;