Write VHDL code for AND gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_or is
Port ( p : in STD_LOGIC;
q : in STD_LOGIC;
r : out STD_LOGIC);
end test_or;

architecture data_flow_test of test_or is
begin
r<= p AND q;
end data_flow_test;