Write VHDL code for 4:1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity mux_test is
port(
A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_test;

architecture beh_test of mux_test is
begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z <= A;
elsif (S0 ='1' and S1 = '0') then
Z <= B;
elsif (S0 ='0' and S1 = '1') then
Z <= C;
else
Z <= D;
end if;
end process;
end beh_test;

Test Bench Code for 4 to 1 Multiplexer:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_mux_test IS
END tb_mux_test;
ARCHITECTURE behavior OF tb_mux_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux_test
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
D : IN std_logic;
S0 : IN std_logic;
S1 : IN std_logic;
Z : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal D : std_logic := '0';
signal S0 : std_logic := '0';
signal S1 : std_logic := '0';
--Outputs
signal Z : std_logic;
BEGIN
uut: mux_test PORT MAP (
A => A,
B => B,
C => C,
D => D,
S0 => S0,
S1 => S1,
Z => Z
);

process
begin
wait for 5 ns;

A <= '1';
B <= '0';
C <= '1';
D <= '0';

S0 <= '0'; S1 <= '0';
wait for 10 ns;

S0 <= '0'; S1 <= '1';
wait for 10 ns;

S0 <= '1'; S1 <= '0';
wait for 10 ns;

S0 <= '1'; S1 <= '1';
wait for 10 ns;

end process;
END;

OUTPUT: