Write VHDL code for Full Adder using Data flow Modeling

https://www.youtube.com/watch?v=PqaPHDLj4Ag


1. VHDL code for full adder using Data flow modeling

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_adder;
architecture test_fa of full_adder is
begin
sum <= A XOR B XOR Cin ;
cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end test_fa;

Test bench Code for Full Adder:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_test_fa IS
END tb_test_fa;
ARCHITECTURE behavior OF tb_test_fa IS
COMPONENT test_Full_Adder
PORT(
x : IN std_logic;
y : IN std_logic;
z : IN std_logic;
sum : OUT std_logic;
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal x : std_logic := '0';
signal y : std_logic := '0';
signal z : std_logic := '0';
--Outputs
signal sum : std_logic;
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test_Full_Adder PORT MAP (
x => x,
y => y,
z => z,
sum => sum,
cout => cout
);-- Stimulus process
process
begin
wait for 5 ns;
x <= '0';
y <= '0';
z <= '0';
wait for 10 ns;
x <= '0';
y <= '0';
z <= '1';
wait for 10 ns;
x <= '0';
y <= '1';
z <= '0';
wait for 10 ns;
x <= '0';
y <= '1';
z <= '1';
wait for 10 ns;
x <= '1';
y <= '0';
z <= '0';
wait for 10 ns;
x <= '1';
y <= '0';
z <= '1';
wait for 10 ns;
x <= '1';
y <= '1';
z <= '0';
wait for 10 ns;
x <= '1';
y <= '1';
z <= '1';
wait for 10 ns;
end process;
END;

OUTPUT: