Flip Flop Conversion

• SR Flip Flop to JK Flip Flop

As told earlier, J and K will be given as external inputs to S and R. As shown in the logic diagram below, S and R will be the outputs of the combinational circuit.

The truth tables for the flip flop conversion are given below. The present state is represented by Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.

For two inputs J and K, there will be eight possible combinations. For each combination of J, K and Qp, the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be obtained by the JK flip flop after the value of Qp. The table is then completed by writing the values of S and R required to get each Qp+1 from the corresponding Qp. That is, the values of S and R that are required to change the state of the flip flop from Qp to Qp+1 are written.

SR Flip Flop to JK Flip Flop

• JK Flip Flop to SR Flip Flop

This will be the reverse process of the above explained conversion. S and R will be the external inputs to J and K. As shown in the logic diagram below, J and K will be the outputs of the combinational circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. The logic diagram is shown below.

A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight combinations are made. For each combination, the corresponding Qp+1 outputs are found ut. The outputs for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the outputs are considered invalid and the J and K values are taken as “don’t cares”.

JK Flip Flop to SR Flip Flop

• SR Flip Flop to D Flip Flop

As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of the flip flop. The four combinations, the logic diagram, conversion table, and the K-map for S and R in terms of D and Qp are shown below.

SR Flip Flop to D Flip Flop

• D Flip Flop to SR Flip FlopD is the actual input of the flip flop and S and R are the external inputs. Eight possible combinations are achieved from the external inputs S, R and Qp. But, since the combination of S=1 and R=1 are invalid, the values of Qp+1 and D are considered as “don’t cares”. The logic diagram showing the conversion from D to SR, and the K-map for D in terms of S, R and Qp are shown below.

  

  D Flip Flop to SR Flip Flop

  • JK Flip Flop to T Flip Flop
  J and K are the actual inputs of the flip flop and T is taken as the external input for conversion. Four combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The conversion table, K-maps, and the logic diagram are given below.

  

  JK Flip Flop to T Flip Flop

  • JK Flip Flop to D Flip Flop
  D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four combinations. J and K are expressed in terms of D and Qp. The four combination conversion table, the K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from JK to D are given below.

• D Flip Flop to JK Flip Flop

In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and Qp make eight possible combinations, as shown in the conversion table below. D is expressed in terms of J, K and Qp.

The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the conversion from D to JK are given in the figure below.

D Flip Flop to JK Flip Flop

Master Slave JK FF

Master-slave JK flip-flop is designed to eliminate the race around condition in JK flip-flop and it is constructed by using two JK flip-flops as shown in the circuit diagram below.

The first flip-flop is called the master, and it is driven by the positive clock cycle. The second flip-flop is called the slave, and it is driven by the negative clock cycle. During the positive clock cycle, master flip-flop gives the intermediate output but slave flip-flop will not give the final output. During the negative clock cycle, slave flip-flop gets activated and copies the previous output of the master flip-flop and produces the final output.

Master-slave JK flip-flop constructed by using NAND gates

State table

Clock	J	K	Q(n+1)	Comments
0	X	X	Q(n)	No change
1	0	0	Q(n)	No change
1	0	1	0	Reset
1	1	0	1	Set
1	1	1	Q(n)’	Toggle

Here, Q(n) is the present state and Q(n+1) is the next state.

Characteristic table

Q(n)	J	K	Q(n+1)
0	0	0	0
0	0	1	0
0	1	0	1
0	1	1	1
1	0	0	1
1	0	1	0
1	1	0	1
1	1	1	0

Excitation table

Q(n)	Q(n+1)	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

Characteristic equation

Q(n+1) = Q(n)'J + Q(n)K'

Flip Flops

Flip Flops:

·         A Flip Flop is a memory element that is capable of storing one bit of information.

·         It is also called as Bistable Multivibrator since it has two stable states either 0 or 1.

 There are following 4 basic types of flip flops-

1.    SR Flip Flop

2.    JK Flip Flop

3.    D Flip Flop

4.    T Flip Flop

SR Flip Flop-

·         SR flip flop is the simplest type of flip flops.

·         It stands for Set Reset flip flop.

·         It is a clocked flip flop.

Construction of SR Flip Flop-

There are following two methods for constructing a SR flip flop-

 

1.    By using NOR latch

2.    By using NAND latch

1. Construction of SR Flip Flop By Using NOR Latch-

This method of constructing SR Flip Flop uses-

·         NOR latch

·         Two AND gates

Logic Circuit-

The logic circuit for SR Flip Flop constructed using NOR latch is as shown below-

2. Construction of SR Flip Flop By Using NAND Latch-

This method of constructing SR Flip Flop uses-

·         NAND latch

·         Two NAND gates

Logic Circuit-

The logic circuit for SR Flip Flop constructed using NAND latch is as shown below-

Logic Symbol-

The logic symbol for SR Flip Flop is as shown below-

Truth Table-

The truth table for SR Flip Flop is as shown below-

The above truth table may be reduced as-

Characteristic Equation-

Draw a k map using the above truth table-

From here-

Q_n+1 = ( SR + SR’ ) ( Q_n +  Q’_n ) + Q_n ( S’R’ + SR’ )

Excitation Table-